An adversary exploits a hardware design flaw in a CPU implementation of transient instruction execution to expose sensitive data and bypass/subvert access control over restricted resources. Typically, the adversary conducts a covert channel attack to target non-discarded microarchitectural changes caused by transient executions such as speculative execution, branch prediction, instruction pipelining, and/or out-of-order execution. The transient execution results in a series of instructions (gadgets) which construct covert channel and access/transfer the secret data.

How do you prevent CAPEC-663?

Implementation: DAWG (Dynamically Allocated Way Guard) - processor cache properly divided between different programs/processes that don't share resources

What weaknesses does CAPEC-663 target?

CAPEC-663 exploits 3 CWE weaknesses, including CWE-1037 (Processor Optimization Removal or Modification of Security-critical Code), CWE-1264 (Hardware Logic with Insecure De-Synchronization between Control and Data Channels), CWE-1303 (Non-Transparent Sharing of Microarchitectural Resources).

How severe is CAPEC-663?

MITRE rates CAPEC-663 as Very High severity with low likelihood of attack.

CAPEC-663: Exploitation of Transient Instruction Execution

Q: How does a Exploitation of Transient Instruction Execution attack work?

It typically unfolds over 5 phases. It begins with: [Survey target application and relevant OS shared code libraries] Adversary identifies vulnerable transient instruction sets and the code/function calls to trigger them as well as instruction sets or code fragments (gadgets) to perform attack.

How the attack works

The phases an attacker typically follows to carry out this attack.

Step 1
Explore
[Survey target application and relevant OS shared code libraries] Adversary identifies vulnerable transient instruction sets and the code/function calls to trigger them as well as instruction sets or code fragments (gadgets) to perform attack.
- Utilize Disassembler and Debugger tools to examine and trace instruction set execution of source code and shared code libraries on a system.
Step 2
Explore
[Explore cache and identify impacts] Utilize tools to understand the impact of transient instruction execution upon address spaces and CPU operations.
- Run OS or application specific tools that examine the contents of cache.
Step 1
Experiment
[Cause conditions for identified transient instruction set execution] Adversary ensures that specific code/instructions of the target process are executed by CPU, so desired transient instructions are executed.
Step 2
Experiment
[Cause specific secret data to be cached from restricted address space] Executed instruction sets (gadgets) in target address space, initially executed via adversary-chosen transient instructions sets, establish covert channel and transfer secret data across this channel to cache.
- Prediction-based - adversary trains CPU to incorrectly predict/speculate conditions for instruction execution to be true, hence executing adversary-chosen transient instructions. These prediction-based methods include: Pattern History Table (PHT)/Input Validation Bypass, Branch Target Buffer (BTB)/Branch Target Injection, Return Stack Buffer (RSB)/Return Address Injection, and Store To Load (STL)/Speculative Store Bypass.
- Exception/Fault-based - adversary has CPU execute transient instructions that raise an exception allowing inaccessible memory space to be accessed via out-of-order execution. These exception/fault-based methods include: Supervisor-only Bypass, Virtual Translation Bypass, System Register Bypass, FPU Register Bypass, Read-only Bypass, Protection Key Bypass, and Bounds Check Bypass.
Step 1
Exploit
[Perform covert channel attack to obtain/access secret data] Adversary process code removes instructions/data from shared cache set, waits for target process to reinsert them back into cache, to identify location of secret data via a timing method. Adversary continuously repeat this process to identify and access entirety of targeted secret data.
- Flush+Reload - adversary frequently flushes targeted memory cache line using a dedicated machine flush instruction, and uses another process to measure time taken for CPU to load victim secret data.
- Evict+Time - adversary causes victim to load target set into cache and measures time for victim process to load this data, setting a baseline. Adversary evicts a specified cache line and causes victim process to execute again, and measures any change in execution time, to determine if cache line was accessed.
- Prime+Probe - adversary primes cache by filling cache line(s) or set(s) with data, after some time victim process evicts this adversary data to replace it with secret data. The adversary then probes/accesses all the previously accessed cache lines detecting cache misses, which determine that their attacker data has been evicted and replaced with secret data from victim process.

CAPEC-663: Exploitation of Transient Instruction Execution

Overview

How the attack works

What the attacker needs

Prerequisites

Skills required

Resources required

Consequences

How to mitigate it

How to detect it

Examples

Frequently asked questions

What is CAPEC-663?

How does a Exploitation of Transient Instruction Execution attack work?

How do you prevent CAPEC-663?

What weaknesses does CAPEC-663 target?

How severe is CAPEC-663?

References

Defend against CAPEC-663

Overview

How the attack works

What the attacker needs

Prerequisites

Skills required

Resources required

Consequences

How to mitigate it

How to detect it

Examples

Related weaknesses

Related attack patterns

Parent

Child

Peer

Can precede

Frequently asked questions

What is CAPEC-663?

How does a Exploitation of Transient Instruction Execution attack work?

How do you prevent CAPEC-663?

What weaknesses does CAPEC-663 target?

How severe is CAPEC-663?

References

Defend against CAPEC-663